The present invention relates to a semiconductor device having a semiconductor memory chip, and to a technique effective for application to a semiconductor device of an MCP (Multi Chip Package) structure in which semiconductor memory chips are laminated and mounted with an TSOP (Thin Small Outline Package).
When two semiconductor memory chips of the same kind are laminated on each other to realize an MCP, bonding pads having the same interface functions such as an address input, a data input/output, etc. are generally bonded to the same lead terminals in both semiconductor memory chips. When the two semiconductor memory chips of the same kind are laminated on each other with their back surfaces being placed face to face to each other at this time, the positions of most bonding pads having the same interface functions are distant from one another where the arrangements or layouts of the bonding pads of the two semiconductor memory chips are exactly the same. Thus, the bonding pads placed in the positions where they are spaced away from one another, must be wire-bonded to a common lead terminal, thus encountering a substantial difficulty in making the bonding pads to intersect other bonding wires without a short circuit.
In order to solve it, mirror-symmetrical chips are formed using new mask patterns obtained by mirror-reversing mask patterns of all layers, or chips changed in wiring layer are formed to make only bonding pads mirror-symmetrical, thereby making it possible to cope with it.
A patent document 1 (Japanese Unexamined Patent Publication No. Hei 7 (1995)-86526) describes the realization of a memory device wherein when two semiconductor memory chips identical to each other are laminated on each other with their back surfaces being placed face to face, interface functions of the same kind are connected to one another as in the case of a connection of address inputs to each other, a connection of data inputs/outputs to each other without sticking to a connection of bonding pads having the same interface functions to one another, and the chips are selected separately, thereby providing double memory capacity without a fear of signal collision.